Single error correcting and double error detecting coding scheme

A new coding technique, for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding, is fewer than all currently available codes for this purpose, except in two cases, when they are almost equal to...

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Veröffentlicht in:Electronics letters Jg. 41; H. 13; S. 1
Hauptverfasser: Lala, P K, Thenappan, P, Anwar, M T
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Stevenage John Wiley & Sons, Inc 23.06.2005
Schlagworte:
Coding
Decoding
Electric circuits
Encoding
Error correction
Error detection
Memory (computers)
Parity
ISSN:0013-5194, 1350-911X
Online-Zugang:Volltext
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Zusammenfassung:A new coding technique, for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding, is fewer than all currently available codes for this purpose, except in two cases, when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction.
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ISSN:0013-5194
1350-911X