Single error correcting and double error detecting coding scheme

A new coding technique, for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding, is fewer than all currently available codes for this purpose, except in two cases, when they are almost equal to...

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Vydané v:Electronics letters Ročník 41; číslo 13; s. 1
Hlavní autori: Lala, P K, Thenappan, P, Anwar, M T
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Stevenage John Wiley & Sons, Inc 23.06.2005
Predmet:
Coding
Decoding
Electric circuits
Encoding
Error correction
Error detection
Memory (computers)
Parity
ISSN:0013-5194, 1350-911X
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Shrnutí:A new coding technique, for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding, is fewer than all currently available codes for this purpose, except in two cases, when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction.
Bibliografia:SourceType-Scholarly Journals-1
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ISSN:0013-5194
1350-911X