Measuring Area-Complexity Using Boolean Difference

For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel a...

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Published in:2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems pp. 245 - 250
Main Authors: Kagliwal, A., Balachandran, S.
Format: Conference Proceeding Journal Article
Language:English
Published: IEEE 01.01.2013
Subjects:
Area measurement
area-complexity
Benchmark testing
Boolean algebra
Boolean difference
Boolean functions
Circuits
Complexity theory
Conferences
Design engineering
Integrated circuits
Logic
Logic gates
logic synthesis
Taylor series
Very large scale integration
ISBN:146734639X, 9781467346399
ISSN:1063-9667
Online Access:Get full text
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Abstract For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions. We demonstrate how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives. We evaluate the metric on circuits from MCNC benchmark suite and a sizeable collection of randomly generated circuits. We compare our metric with existing techniques based on literal-count and BDD properties. We show that the new area-complexity measure is accurate within 10% of the actual number of gates synthesized using ABC as opposed to at least 100% and 15% for the metrics based on literal-count and BDD properties respectively. We also show the robustness of our metric across three different gate-libraries.
AbstractList For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like literal count, number of primary input/outputs, etc. have been used in the past as area-complexity metrics. In this paper, we propose a novel area-complexity measure using the theory of Boolean difference and Taylor expansion for Boolean functions. We demonstrate how to capture the area-complexity of a Boolean function using the complexity of its Boolean derivatives. We evaluate the metric on circuits from MCNC benchmark suite and a sizeable collection of randomly generated circuits. We compare our metric with existing techniques based on literal-count and BDD properties. We show that the new area-complexity measure is accurate within 10% of the actual number of gates synthesized using ABC as opposed to at least 100% and 15% for the metrics based on literal-count and BDD properties respectively. We also show the robustness of our metric across three different gate-libraries.
Author Balachandran, S.
Kagliwal, A.
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Snippet For a combinational circuit, area-complexity is a measure that estimates the logic area of the circuit without mapping to logic gates. Several measures like...
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StartPage 245
SubjectTerms Area measurement
area-complexity
Benchmark testing
Boolean algebra
Boolean difference
Boolean functions
Circuits
Complexity theory
Conferences
Design engineering
Integrated circuits
Logic
Logic gates
logic synthesis
Taylor series
Very large scale integration
Title Measuring Area-Complexity Using Boolean Difference
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