A vector memory system based on wafer-scale integrated memory arrays

The paper proposes a memory architecture called Wafer-scale Interconnected Memory Array (WIMA), which is intended to replace ultra-high-density monolithic DRAM ICs. This architecture employs the high-performance interconnects provided by multichip module technology, the cache-embedding concept, and...

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Bibliographic Details
Published in:Computer Design: VLSI in Computers and Processors (ICCD '93 pp. 284 - 288
Main Author: Chiueh, T.-C.
Format: Conference Proceeding Journal Article
Language:English
Published: IEEE Comput. Soc. Press 1993
Subjects:
Bandwidth
Costs
Delay
Hardware
Interleaved codes
Memory architecture
Parallel processing
Random access memory
Read-write memory
Supercomputers
ISBN:0818642300, 9780818642302
Online Access:Get full text
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Summary:The paper proposes a memory architecture called Wafer-scale Interconnected Memory Array (WIMA), which is intended to replace ultra-high-density monolithic DRAM ICs. This architecture employs the high-performance interconnects provided by multichip module technology, the cache-embedding concept, and prime degree interleaving to expose the DRAM's internal parallelism not exploitable by monolithic DRAMs. Using WIMA modules as the basic building blocks, a high-bandwidth, low latency, and low cost vector memory system is developed that supports parallelism among multiple vector access streams. To mask the long start-up latencies, vector memory accesses are architectured to be split-phased. To alleviate the performance impact of bank conflicts, prime degree memory interleaving is adopted. The major contribution of this work is the development of a novel indexing mechanism for prime degree interleaving, which takes at most two integer divisions for each logical vector memory access.< >
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ISBN:0818642300
9780818642302
DOI:10.1109/ICCD.1993.393365