A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications

This paper presents the design, development and implementation of a novel and efficient Serial Peripheral Interface (SPI)-enabled Rivest-Shamir-Adleman (RSA) Encryption/Decryption Crypto Accelerator tailored for real-time applications. The RSA Crypto Accelerator was developed using the Semiconductor...

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Bibliographic Details

Published in:	International Symposium on VLSI Design and Test pp. 1 - 6
Main Authors:	Kolagatla, Venkata Reddy, Raveendran, Aneesh, Desalphine, Vivian
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.09.2024
Subjects:	ASIC Implementations Clocks Crypto Accelerators Cryptography Foundries Life estimation Power demand Public Key Cryptography Real-time systems RSA Crypto System SPI Protocol SPICE Synchronization Very large scale integration
ISSN:	2768-0800
Online Access:	Get full text
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