FPGA Implementation of Range Migration Algorithm for Synthetic Aperture Radar Using Simulink HDL Coder

The millimeter-wave synthetic aperture radar echo data processing is a vital step in target reconstruction, and this phase is inherently time-consuming, demanding significant computational resources. To expedite the reconstruction process, Field-Programmable Gate Arrays (FPGA) can be employed. Never...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:Digest - IEEE Antennas and Propagation Society. International Symposium (1995) s. 713 - 714
Hlavní autori: Meng, Yang, Yang, Haoyi, Chen, Bocheng, Chen, Guoping, Qing, Anyong
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 14.07.2024
Predmet:
Approximation algorithms
Computer architecture
fast Fourier transform (FFT)
FPGA
Hardware
HDL Coder
Millimeter wave radar
Radar antennas
RMA
Simulink
Software packages
synthetic aperture radar (SAR)
VHDL
ISSN:1947-1491
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:The millimeter-wave synthetic aperture radar echo data processing is a vital step in target reconstruction, and this phase is inherently time-consuming, demanding significant computational resources. To expedite the reconstruction process, Field-Programmable Gate Arrays (FPGA) can be employed. Nevertheless, utilizing FPGA for implementation often entails grappling with complex hardware description languages such as Verilog or VHDL, which are difficult and time-consuming to develop. To overcome these challenges, a hardware architecture based on the range migration algorithm (RMA) is proposed in this paper. We utilize the Simulink HDL Coder toolbox to encapsulate the algorithm into an IP Core, subsequently verifying it on the Xilinx XC7Z020. The test results show that operating at a clock frequency of 100MHz, target reconstruction with original data of size 256×151×64 requires approximately 26.74 ms. This represents a notable acceleration, being about 7.2 times faster than CPU processing in Matlab.
ISSN:1947-1491
DOI:10.1109/AP-S/INC-USNC-URSI52054.2024.10686571