Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has be...

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Vydáno v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 20; číslo 11; s. 1938 - 1950
Hlavní autoři:	Zhang, Xinmiao, Cai, Fang, Lin, Shu
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.11.2012 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithm design and analysis Algorithms Applied sciences Binary system Circuit properties Codes Coding Complexity theory Decoders Decoding Design engineering Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoding Exact sciences and technology Gain Integrated circuits Iterative decoding Iterative majority-logic decoding Low density parity check codes low-density parity-check (LDPC) codes Niobium non-binary Parity check codes partial-parallel Reliability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Very large scale integration VLSI Performance evaluation partial-parallel VLSI circuit Error estimation VLSI Coding circuit Majority logic Iterative method Decoding circuit Decoding non-binary Algorithm Binary code low-density parity-check (LDPC) codes Coding Integrated circuit Iterative majority-logic decoding Parity check codes Error correction Reliability Time complexity Gain Parity check
ISSN:	1063-8210, 1557-9999
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Shrnutí:	Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E-)IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 ObjectType-Article-2 ObjectType-Feature-1 content type line 23
ISSN:	1063-8210 1557-9999
DOI:	10.1109/TVLSI.2011.2164951