Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs

This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2 m ) . By introducing the common expression sharing and...

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Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 18; číslo 7; s. 1057 - 1066
Hlavní autori:	Gang Zhou, Michalik, Harald, Hinsenkamp, László
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York, NY IEEE 01.07.2010 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Algorithm design and analysis Application specific integrated circuits Applied sciences Bit parallel multiplier Circuit properties Complexity Computer aided design Design automation Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Elliptic curve cryptography Exact sciences and technology Field programmable gate arrays field-programmable gate array (FPGA) finite field Galois fields Integrated circuits Iterative methods Karatsuba-Ofman multiplier (KOM) Multipliers NIST Optimization polynomial basis Polynomials Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices System performance Table lookup Very large scale integration Lower bound Finite field Arithmetic circuit Circuit design Iterative method Field programmable gate array Bit parallel multiplier Algorithm field-programmable gate array (FPGA) Implementation Look up table Karatsuba-Ofman multiplier (KOM) Integrated circuit polynomial basis Custom circuit Multiplying circuits Computer aided design
ISSN:	1063-8210, 1557-9999
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