Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs

This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2 m ) . By introducing the common expression sharing and...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems Jg. 18; H. 7; S. 1057 - 1066
Hauptverfasser: Gang Zhou, Michalik, Harald, Hinsenkamp, László
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York, NY IEEE 01.07.2010
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithm design and analysis
Application specific integrated circuits
Applied sciences
Bit parallel multiplier
Circuit properties
Complexity
Computer aided design
Design automation
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Elliptic curve cryptography
Exact sciences and technology
Field programmable gate arrays
field-programmable gate array (FPGA)
finite field
Galois fields
Integrated circuits
Iterative methods
Karatsuba-Ofman multiplier (KOM)
Multipliers
NIST
Optimization
polynomial basis
Polynomials
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
System performance
Table lookup
Very large scale integration
Lower bound
Finite field
Arithmetic circuit
Circuit design
Iterative method
Field programmable gate array
Bit parallel multiplier
Algorithm
field-programmable gate array (FPGA)
Implementation
Look up table
Karatsuba-Ofman multiplier (KOM)
Integrated circuit
polynomial basis
Custom circuit
Multiplying circuits
Computer aided design
ISSN:1063-8210, 1557-9999
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2 m ) . By introducing the common expression sharing and the complexity analysis on odd-term polynomials, we achieve a lower gate bound than previous ASIC discussions. The analysis is extended by using 4-input/6-input lookup tables (LUT) on FPGAs. For an arbitrary bit-depth, the optimum iteration step is shown. The optimum iteration steps differ for ASICs, 4-input LUT-based FPGAs and 6-input LUT-based FPGAs. We evaluate the LUT complexity and area-time product tradeoffs on FPGAs with different computer-aided design (CAD) tools. Furthermore, the experimental results on FPGAs for bit parallel modular multipliers are shown and compared with previous implementations. To the best of our knowledge, our bit parallel multipliers consume the least resources among known FPGA implementations to date.
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ObjectType-Article-1
ObjectType-Feature-2
content type line 23
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2020088