A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES...

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Veröffentlicht in:	Journal of Parallel and Distributed Computing Jg. 106; S. 106 - 120
Hauptverfasser:	At, Nuray, Beuchat, Jean-Luc, Okamoto, Eiji, San, Ismail, Yamazaki, Teppei
Format:	Journal Article
Sprache:	Englisch Japanisch
Veröffentlicht:	Elsevier Inc 01.08.2017 Elsevier BV
Schlagworte:	Ciphers Coprocessors Cryptographic Hash Functions Cryptography Embedded Systems Field Programmable Gate Arrays Ciphers Embedded systems Cryptography Cryptographic hash functions Field programmable gate arrays Coprocessors
ISSN:	0743-7315, 1096-0848
Online-Zugang:	Volltext
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