A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES...

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Bibliographic Details
Published in:Journal of Parallel and Distributed Computing Vol. 106; pp. 106 - 120
Main Authors: At, Nuray, Beuchat, Jean-Luc, Okamoto, Eiji, San, Ismail, Yamazaki, Teppei
Format: Journal Article
Language:English
Japanese
Published: Elsevier Inc 01.08.2017
Elsevier BV
Subjects:
Ciphers
Coprocessors
Cryptographic Hash Functions
Cryptography
Embedded Systems
Field Programmable Gate Arrays
Ciphers
Embedded systems
Cryptography
Cryptographic hash functions
Field programmable gate arrays
Coprocessors
ISSN:0743-7315, 1096-0848
Online Access:Get full text
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Summary:This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security (i.e. 128-, 192-, and 256-bit encryption keys; 256- and 512-bit message digests). A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput (up to 217 Mbits/s and 92 Mbits/s for encryption and hashing, respectively). The proposed coprocessor is well-suited for resource-constrained embedded systems, where several security protocols rely only on block ciphers and hash functions. One can exploit the design philosophy presented in this paper in order to design a unified architecture for other algorithms. •An 8-bit coprocessor for the AES and Grøstl at all levels of security is proposed.•An implementation of the AES and Grøstl with a single instruction set architecture is presented.•The ALU is deeply pipelined to achieve a high clock frequency.•A careful scheduling allows us to avoid data dependency issues.
ISSN:0743-7315
1096-0848
DOI:10.1016/j.jpdc.2017.01.029