Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms

Fully pipelined parallel architectures are derived for high-throughput and reduced-hardware realization of prime-factor cyclic convolution using hardware-efficient modules for short-length rectangular transform (RT). Moreover, a new approach is proposed for the computation of block pseudocyclic conv...

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Bibliographic Details
Published in:	IEEE transactions on circuits and systems for video technology Vol. 18; no. 10; pp. 1422 - 1431
Main Author:	Meher, P.K.
Format:	Journal Article
Language:	English
Published:	New York, NY IEEE 01.10.2008 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Applied sciences Architecture Block-cyclic convolution Blocking Complexity Computation Computational efficiency Computer architecture Concurrent computing Convolution cyclic convolution Design. Technologies. Operation analysis. Testing Discrete cosine transforms Discrete Fourier transforms Electronics Exact sciences and technology Fast Fourier transforms Finite impulse response filter Hardware Integrated circuits Iterative algorithms pseudocyclic convolution Reduction Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Studies Systems, networks and services of telecommunications systolic array Telecommunications Telecommunications and information theory Transmission and modulation (techniques and equipments) Very large scale integration very large-scale integration (VLSI) VLSI circuit Segmentation Block-cyclic convolution Information rate Parallel architectures Systolic network Algorithm Information transmission Implementation Pipeline processing pseudocyclic convolution Convolution Computation error cyclic convolution Integrated circuit systolic array Delay time very large-scale integration (VLSI)
ISSN:	1051-8215, 1558-2205
Online Access:	Get full text
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