Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms

Fully pipelined parallel architectures are derived for high-throughput and reduced-hardware realization of prime-factor cyclic convolution using hardware-efficient modules for short-length rectangular transform (RT). Moreover, a new approach is proposed for the computation of block pseudocyclic conv...

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Vydáno v:	IEEE transactions on circuits and systems for video technology Ročník 18; číslo 10; s. 1422 - 1431
Hlavní autor:	Meher, P.K.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.10.2008 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithms Applied sciences Architecture Block-cyclic convolution Blocking Complexity Computation Computational efficiency Computer architecture Concurrent computing Convolution cyclic convolution Design. Technologies. Operation analysis. Testing Discrete cosine transforms Discrete Fourier transforms Electronics Exact sciences and technology Fast Fourier transforms Finite impulse response filter Hardware Integrated circuits Iterative algorithms pseudocyclic convolution Reduction Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Studies Systems, networks and services of telecommunications systolic array Telecommunications Telecommunications and information theory Transmission and modulation (techniques and equipments) Very large scale integration very large-scale integration (VLSI) VLSI circuit Segmentation Block-cyclic convolution Information rate Parallel architectures Systolic network Algorithm Information transmission Implementation Pipeline processing pseudocyclic convolution Convolution Computation error cyclic convolution Integrated circuit systolic array Delay time very large-scale integration (VLSI)
ISSN:	1051-8215, 1558-2205
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Shrnutí:	Fully pipelined parallel architectures are derived for high-throughput and reduced-hardware realization of prime-factor cyclic convolution using hardware-efficient modules for short-length rectangular transform (RT). Moreover, a new approach is proposed for the computation of block pseudocyclic convolution using a block cyclic convolution of equal length along with some correction terms, so that the block pseudocyclic representation of cyclic convolution for non-prime-factor-length ( N = rP , when r and P are not mutually prime) could be computed efficiently using the algorithms and architectures of short-length cyclic convolutions. Low-complexity algorithms are derived for efficient computation of those error terms, and overall complexities of the proposed technique are estimated for r =2, 3, 4, 6, 8 and 9. The proposed algorithms are used further to design high-throughput and reduced-hardware structures for cyclic convolution where the cofactors are not relatively prime. The proposed structures for high-throughput implementation are found to offer a reduction of nearly 50%-75% of area-delay product over the existing structures for several convolution-lengths. Low-complexity structures for input/output addition units of short length convolutions are derived and used them along with high-throughput modules for hardware-efficient realization of multifactor convolution, which offers nearly 25%-75% reduction of area-delay complexity over the existing structures for various non-prime-factor length convolutions.
Bibliografie:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 ObjectType-Article-1 ObjectType-Feature-2 content type line 23
ISSN:	1051-8215 1558-2205
DOI:	10.1109/TCSVT.2008.2004918