Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms
Fully pipelined parallel architectures are derived for high-throughput and reduced-hardware realization of prime-factor cyclic convolution using hardware-efficient modules for short-length rectangular transform (RT). Moreover, a new approach is proposed for the computation of block pseudocyclic conv...
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| Vydané v: | IEEE transactions on circuits and systems for video technology Ročník 18; číslo 10; s. 1422 - 1431 |
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| Hlavný autor: | |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
New York, NY
IEEE
01.10.2008
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Predmet: | |
| ISSN: | 1051-8215, 1558-2205 |
| On-line prístup: | Získať plný text |
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