Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

We propose a network-on-chip (NoC)-based whole system design, whose communication architecture is compatible with the advanced microcontroller bus architecture advanced extensible interface 4 (AXI4) protocol and supports high-performance multiple quality-of-service (QoS) schemes. In our system, the...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 41; H. 5; S. 1523 - 1536
Hauptverfasser:	Wang, Boqian, Lu, Zhonghai
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.05.2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Advanced extensible interface 4 (AXI4) Communication architectures Communications systems Communications traffic Computer architecture Converters Format Inheritance mechanisms Integrated circuit design Integrated circuit interconnections Internet protocols Microcontrollers Multiple quality Network architecture Network latency Network-on-chip network-on-chip (NoC) Network-on-chip architectures NoC architectures Packet latencies Packets (communication) Proposed architectures Protocols Provisioning Quality of service quality of service (QoS) Quality of service architectures Regulation Routing Servers System on chip system-on-chip (SoC) Systems design Time division multiplexing
ISSN:	0278-0070, 1937-4151, 1937-4151
Online-Zugang:	Volltext
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