Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck

The central unit of a Viterbi decoder is a data-dependent feedback loop which performs an add-compare-select (ACS) operation. This nonlinear recursion is the only bottleneck for a high-speed parallel implementation. A linear scale solution (architecture) is presented which allows the implementation...

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Vydané v:	IEEE transactions on communications Ročník 37; číslo 8; s. 785 - 790
Hlavní autori:	Fettweis, G., Meyr, H.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York, NY IEEE 01.08.1989 Institute of Electrical and Electronics Engineers
Predmet:	Applied sciences Coding, codes Computer architecture Decoding Dynamic programming Exact sciences and technology Feedback loop Hardware Information, signal and communications theory Markov processes Recursive estimation Signal and communications theory Systolic arrays Telecommunications and information theory Throughput Viterbi algorithm System architecture Bottleneck Parallel algorithm Flow rate Decoding Systolic network Viterbi decoding
ISSN:	0090-6778
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