Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck

The central unit of a Viterbi decoder is a data-dependent feedback loop which performs an add-compare-select (ACS) operation. This nonlinear recursion is the only bottleneck for a high-speed parallel implementation. A linear scale solution (architecture) is presented which allows the implementation...

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Veröffentlicht in:IEEE transactions on communications Jg. 37; H. 8; S. 785 - 790
Hauptverfasser: Fettweis, G., Meyr, H.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York, NY IEEE 01.08.1989
Institute of Electrical and Electronics Engineers
Schlagworte:
Applied sciences
Coding, codes
Computer architecture
Decoding
Dynamic programming
Exact sciences and technology
Feedback loop
Hardware
Information, signal and communications theory
Markov processes
Recursive estimation
Signal and communications theory
Systolic arrays
Telecommunications and information theory
Throughput
Viterbi algorithm
System architecture
Bottleneck
Parallel algorithm
Flow rate
Decoding
Systolic network
Viterbi decoding
ISSN:0090-6778
Online-Zugang:Volltext
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Zusammenfassung:The central unit of a Viterbi decoder is a data-dependent feedback loop which performs an add-compare-select (ACS) operation. This nonlinear recursion is the only bottleneck for a high-speed parallel implementation. A linear scale solution (architecture) is presented which allows the implementation of the Viterbi algorithm (VA) despite the fact that it contains a data-dependent decision feedback loop. For a fixed processing speed it allows a linear speedup in the throughput rate by a linear increase in hardware complexity. A systolic array implementation is discussed for the add-compare-select unit of the VA. The implementation of the survivor memory is considered. The method for implementing the algorithm is based on its underlying finite state feature. Thus, it is possible to transfer this method to other types of algorithms which contain a data-dependent feedback loop and have a finite state property.< >
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ISSN:0090-6778
DOI:10.1109/26.31176