XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated...

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Vydané v:	IEEE journal of solid-state circuits Ročník 55; číslo 6; s. 1733 - 1743
Hlavní autori:	Yin, Shihui, Jiang, Zhewei, Seo, Jae-Sun, Seok, Mingoo
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.06.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Accuracy Analog to digital conversion Analog to digital converters Artificial neural networks Binary weights CMOS Complexity theory Computation Computer architecture deep neural networks (DNNs) Energy conversion efficiency Energy efficiency ensemble learning Hardware in-memory computing (IMC) Neural networks Random access memory SRAM Static random access memory System-on-chip ternary activations Transistors Voltage dividers
ISSN:	0018-9200, 1558-173X
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