A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding

Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thu...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology Vol. 20; no. 6; pp. 848 - 860
Main Authors: KIM, Jaemoon, KYUNG, Chong-Min
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.06.2010
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Applied sciences
Bandwidth
Clocks
Coding
Compressing
Decoding
Embedded compression (EC)
Errors
Exact sciences and technology
Handles
Hardware
High definition video
Image coding
Image processing
Information, signal and communications theory
Lossless
lossless compression
memory bandwidth
Pixels
Prediction methods
Signal processing
significant bit truncation (SBT)
Studies
Systems, networks and services of telecommunications
Telecommunications
Telecommunications and information theory
Throughput
Transmission and modulation (techniques and equipments)
Video coding
Video sequences
Video coding
Lower bound
Averaging method
Lossless circuit
High resolution
Video signal
Lossless compression
Information rate
Clock
Algorithm
Information transmission
Implementation
Video signal processing
memory bandwidth
Compression ratio
Image sequence
Embedded compression (EC)
significant bit truncation (SBT)
ISSN:1051-8215, 1558-2205
Online Access:Get full text
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Description
Summary:Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thus far. In this paper, a lossless EC algorithm for HD video sequences and related hardware architecture is proposed. The proposed algorithm consists of two steps. The first is a hierarchical prediction method based on pixel averaging and copying. The second step involves significant bit truncation (SBT) which encodes prediction errors in a group with the same number of bits so that the multiple prediction errors are decoded in a clock cycle. The theoretical lower bound of the compression ratio of the SBT coding was also derived. Experimental results have shown a 60% reduction of memory bandwidth on average. Hardware implementation results have shown that a throughput of 14.2 pixels/cycle can be achieved with 36 K gates, which is sufficient to handle HD-size video sequences in real time.
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ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2010.2045923