Parallel decoding cyclic burst error correcting codes

Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic...

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Veröffentlicht in:IEEE transactions on computers Jg. 54; H. 1; S. 87 - 92
Hauptverfasser: Umanesan, G., Fujiwara, E.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.01.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Bursting
Channels
Combinational logic circuits
companion matrix
Cyclic codes
Decoding
Error correcting codes
Error correction coding
Fire codes
High speed
Index Terms- Cyclic burst error correcting codes
Linear feedback shift registers
Logic
Matrix multiplication
parallel decoding
Shift registers
ISSN:0018-9340, 1557-9956
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Zusammenfassung:Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic.
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2005.9