Parallel decoding cyclic burst error correcting codes

Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic...

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Vydáno v:	IEEE transactions on computers Ročník 54; číslo 1; s. 87 - 92
Hlavní autoři:	Umanesan, G., Fujiwara, E.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.01.2005 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Bursting Channels Combinational logic circuits companion matrix Cyclic codes Decoding Error correcting codes Error correction coding Fire codes High speed Index Terms- Cyclic burst error correcting codes Linear feedback shift registers Logic Matrix multiplication parallel decoding Shift registers
ISSN:	0018-9340, 1557-9956
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Popis
Shrnutí:	Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic.
Bibliografie:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23
ISSN:	0018-9340 1557-9956
DOI:	10.1109/TC.2005.9