Design of self-testable wafer-scale processor arrays

A technique for designing self-testable wafer-scale arrays is presented. Faulty and Fault-free cells (processors, PEs) are indentified in distributed fashion without providing correct responses from the outside. It uses both local comparisons and dissemination of the comparison results. Faults in di...

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Vydané v:	International journal of electronics Ročník 69; číslo 5; s. 665 - 671
Hlavný autor:	CHOI, YOON-HWA
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	London Taylor & Francis Group 01.11.1990 Taylor & Francis
Predmet:	Applied sciences Electronics Exact sciences and technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Processor Circuit design Test Network Defect Algorithm Wafer
ISSN:	0020-7217, 1362-3060
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