Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory
As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low e...
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| Veröffentlicht in: | IEEE communications letters Jg. 19; H. 3; S. 327 - 330 |
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| Format: | Journal Article |
| Sprache: | Englisch |
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New York
IEEE
01.03.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1089-7798, 1558-2558 |
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| Abstract | As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor. |
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| AbstractList | As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor. |
| Author | Shin-Lin Shieh |
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| Cites_doi | 10.1109/TIT.2004.831841 10.1109/ITA.2014.6804221 10.1109/LCOMM.2013.031913.130142 10.1109/LCOMM.2003.814716 10.1109/26.494301 10.1109/GLOCOMW.2010.5700263 |
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| Keywords | flash memory error floor concatenated code BCH code Low-density parity-check code |
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| StartPage | 327 |
| SubjectTerms | Ash Bit error rate Decoding Encoding Iterative decoding Reliability |
| Title | Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory |
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