Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory

As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low e...

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Bibliographic Details
Published in:IEEE communications letters Vol. 19; no. 3; pp. 327 - 330
Main Author: Shieh, Shin-Lin
Format: Journal Article
Language:English
Published: New York IEEE 01.03.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Ash
Bit error rate
Decoding
Encoding
Iterative decoding
Reliability
flash memory
error floor
concatenated code
BCH code
Low-density parity-check code
ISSN:1089-7798, 1558-2558
Online Access:Get full text
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Summary:As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor.
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ISSN:1089-7798
1558-2558
DOI:10.1109/LCOMM.2015.2391260