Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip
We have presented an optimal buffer sizing and buffer insertion methodology which uses stochastic models of the architecture and Continuous Time Markov Decision Processes CTMDPs. Such amethodology is useful in managing the scarce buffer resources available on chip as compared to network based data c...
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| Published in: | Design, Automation and Test in Europe pp. 826 - 827 |
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| Main Authors: | , , |
| Format: | Conference Proceeding |
| Language: | English |
| Published: |
Washington, DC, USA
IEEE Computer Society
07.03.2005
IEEE |
| Series: | ACM Conferences |
| Subjects: |
Hardware
> Electronic design automation
> High-level and register-transfer level synthesis
> Datapath optimization
Mathematics of computing
> Probability and statistics
> Probabilistic representations
> Markov networks
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| ISBN: | 9780769522883, 0769522882 |
| ISSN: | 1530-1591 |
| Online Access: | Get full text |
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| Summary: | We have presented an optimal buffer sizing and buffer insertion methodology which uses stochastic models of the architecture and Continuous Time Markov Decision Processes CTMDPs. Such amethodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The modeling of this problem in terms of a CT-MDP framework lead to a nonlinear formulation due to usage of bridges in the bus architecture. We present a methodology to split the problem into several smaller though linear systems and we then solve these subsystems. |
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| Bibliography: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
| ISBN: | 9780769522883 0769522882 |
| ISSN: | 1530-1591 |
| DOI: | 10.1109/DATE.2005.86 |

