Joint design-time and post-silicon optimization for digitally tuned analog circuits

Joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric...

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Vydané v:	2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers s. 725 - 730
Hlavní autori:	Wei Yao, Yiyu Shi, Lei He, Pamarti, S.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.11.2009
Predmet:	Analog circuits Capacitance Circuit optimization Constraint optimization Design optimization Optimization methods Phase locked loops Space exploration Transmitters Tunable circuits and devices
ISSN:	1092-3152
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