Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors for implementing a four error correcting (127,99) BCH error control code decoder

The Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors are compared on the basis of their use in implementing a four error correcting (127,99) BCH code decoder. The code is being used as a basis for comparing various decoder implementations. Algorithms for efficient micr...

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Vydáno v:Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing s. 345 - 349
Hlavní autoři: Weeks, W.B., Little, W.D., Bhargava, V.K., Gulliver, T.A.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 1989
Témata:
Assembly
Bit rate
Decoding
Digital signal processors
Error correction codes
Instruments
Microprocessors
Signal processing algorithms
Testing
Time factors
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Shrnutí:The Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors are compared on the basis of their use in implementing a four error correcting (127,99) BCH code decoder. The code is being used as a basis for comparing various decoder implementations. Algorithms for efficient microprocessor implementations of a decoder are presented. The ability to implement time-critical steps in these algorithms is the basis for comparing the DSP56000 and the TMS320C25. The DSP56000's comparatively general-purpose architecture and certain unique features provide a higher bit rate decoder than can be implemented on the TMS320C25. Assembly language programs have been written and tested for performance and timing using IBM PC-based simulators of the processors. A complete decoder has been implemented on the DSP56000, achieving an average bit rate in excess of 1 million b/s.< >
DOI:10.1109/PACRIM.1989.48373