Modulo M multiplication-addition: algorithms and FPGA implementation

Variants of a modular multiplication algorithm originally due to Koc and Hung, that are especially suited for FPGA implementation, and that allow to compute (XY+W) modulo M, where there is no need to know M at design-time, are presented. Some results obtained on a Xilinx Virtex-E FPGA, are shown.

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Vydané v:Electronics letters Ročník 40; číslo 11; s. 1
Hlavní autori: Beuchat, J-L, Muller, J-M
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Stevenage John Wiley & Sons, Inc 27.05.2004
Predmet:
Algorithms
Field programmable gate arrays
Modular
Multiplication
ISSN:0013-5194, 1350-911X
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Shrnutí:Variants of a modular multiplication algorithm originally due to Koc and Hung, that are especially suited for FPGA implementation, and that allow to compute (XY+W) modulo M, where there is no need to know M at design-time, are presented. Some results obtained on a Xilinx Virtex-E FPGA, are shown.
Bibliografia:SourceType-Scholarly Journals-1
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ISSN:0013-5194
1350-911X