Speculative multithreading architectures
Much emphasis is now placed on architectures, such as the chip-multiprocessor (CMP), for exploiting thread-level parallelism in an application. Here, speculation may be employed to execute applications that cannot be parallelized efficiently. Unfortunately, current approaches either use limited hard...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Dissertation |
| Sprache: | Englisch |
| Veröffentlicht: |
ProQuest Dissertations & Theses
01.01.1998
|
| Schlagworte: | |
| ISBN: | 0599106131, 9780599106130 |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | Much emphasis is now placed on architectures, such as the chip-multiprocessor (CMP), for exploiting thread-level parallelism in an application. Here, speculation may be employed to execute applications that cannot be parallelized efficiently. Unfortunately, current approaches either use limited hardware support that permit a restricted communication mechanism between processors or use a large amount of speculation hardware. In this thesis, we show that wide- issue dynamic processors that will soon populate CMPs would make fast communication at the register level a requirement for high performance. Consequently, we propose an effective yet modest hardware that supports communication and synchronization of registers between on- chip processors. Furthermore, we propose hardware that handles memory dependence violations that may occur in a speculative execution mode. We also present the compiler support that enables identification of threads from sequential binaries. We show how the software-hardware approach enables effective speculative execution of a sequential binary on a CMP architecture without source re-compilation. Unlike the CMP approach, the Simultaneous Multithreading (SMT) architecture allows complete flexibility in resource sharing and avoids resource wastage when there is lack of threads. Unfortunately, this approach is centralized. Consequently, we explore a hybrid approach in our thesis. We show that a limited level of simultaneous multithreading is able to capture most of the performance benefits of the fully centralized approach while, at the same time, allows a decentralized design. Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven Simulations (EDS) where the processor component of the system is not fully modeled. However, using direct-execution to model a superscalar processor has been considered an open problem. In the last part of the thesis, we propose a novel direct-execution framework that allows accurate simulation of wide-issue superscalar processors for both a uni- and multi-processor configuration. |
|---|---|
| Bibliographie: | SourceType-Dissertations & Theses-1 ObjectType-Dissertation/Thesis-1 content type line 12 |
| ISBN: | 0599106131 9780599106130 |