Memory Hierarchy and Virtual Memory Management

Memory is a temporary place for storing programs. It is commonly implemented with dynamic random access memory (DRAM). This chapter describes the memory structures, cache organizations, virtual memory management, and translation lookaside buffer (TLB) organizations. The mechanism of the TLB‐based mi...

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Vydané v:	Computer Principles and Design in Verilog HDL s. 353 - 385
Hlavní autori:	Li, Yamin, Tsinghua University Press
Médium:	Kapitola
Jazyk:	English
Vydavateľské údaje:	Singapore Wiley 2015 John Wiley & Sons, Incorporated John Wiley & Sons, Ltd
Predmet:	cache block replacement algorithms content addressable memory dynamic random access memory microprocessor without interlocked pipeline stages ROM static random access memory translation lookaside buffer Verilog HDL virtual memory management
ISBN:	1118841093, 9781118841099
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