Memory Hierarchy and Virtual Memory Management

Memory is a temporary place for storing programs. It is commonly implemented with dynamic random access memory (DRAM). This chapter describes the memory structures, cache organizations, virtual memory management, and translation lookaside buffer (TLB) organizations. The mechanism of the TLB‐based mi...

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Vydáno v:Computer Principles and Design in Verilog HDL s. 353 - 385
Hlavní autoři: Li, Yamin, Tsinghua University Press
Médium: Kapitola
Jazyk:angličtina
Vydáno: Singapore Wiley 2015
John Wiley & Sons, Incorporated
John Wiley & Sons, Ltd
Témata:
cache block replacement algorithms
content addressable memory
dynamic random access memory
microprocessor without interlocked pipeline stages
ROM
static random access memory
translation lookaside buffer
Verilog HDL
virtual memory management
ISBN:1118841093, 9781118841099
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Shrnutí:Memory is a temporary place for storing programs. It is commonly implemented with dynamic random access memory (DRAM). This chapter describes the memory structures, cache organizations, virtual memory management, and translation lookaside buffer (TLB) organizations. The mechanism of the TLB‐based microprocessor without interlocked pipeline stages (MIPS) virtual memory management is also introduced. There are many types of memory, but the chapter discusses the following four types of memory: static random access memory (SRAM), DRAM, read‐only memory (ROM), and content addressable memory (CAM). The parameters for designing a cache include the total cache size, block size, cache mapping methods, cache block replacement algorithms, cache write strategies in case of a cache hit, and cache write policies in case of a cache miss. The chapter explains these parameters in detail. It also gives the Verilog HDL code for a design example of an eight‐entry TLB.
ISBN:1118841093
9781118841099
DOI:10.1002/9781118841105.ch11