Input/Output Interface Controller Design in Verilog HDL

This chapter first introduces the basic technologies related to input/output (I/O) interface design, and describes the methods of data error detection and correction. It then gives some I/O interface design examples, including the universal asynchronous receiver transmitter (UART), personal system/2...

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Bibliographic Details

Published in:	Computer Principles and Design in Verilog HDL pp. 443 - 508
Main Authors:	Li, Yamin, Tsinghua University Press
Format:	Book Chapter
Language:	English
Published:	Singapore Wiley 2015 John Wiley & Sons, Incorporated John Wiley & Sons, Ltd
Subjects:	cyclic redundancy check extended hamming code i/o interface design inter integrated circuit serial bus parity check peripheral component interconnect parallel bus personal system/2 keyboard and mouse universal asynchronous receiver transmitter verilog hdl video graphics array
ISBN:	1118841093, 9781118841099
Online Access:	Get full text
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