Input/Output Interface Controller Design in Verilog HDL

This chapter first introduces the basic technologies related to input/output (I/O) interface design, and describes the methods of data error detection and correction. It then gives some I/O interface design examples, including the universal asynchronous receiver transmitter (UART), personal system/2...

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Vydáno v:Computer Principles and Design in Verilog HDL s. 443 - 508
Hlavní autoři: Li, Yamin, Tsinghua University Press
Médium: Kapitola
Jazyk:angličtina
Vydáno: Singapore Wiley 2015
John Wiley & Sons, Incorporated
John Wiley & Sons, Ltd
Témata:
cyclic redundancy check
extended hamming code
i/o interface design
inter integrated circuit serial bus
parity check
peripheral component interconnect parallel bus
personal system/2 keyboard and mouse
universal asynchronous receiver transmitter
verilog hdl
video graphics array
ISBN:1118841093, 9781118841099
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Popis
Shrnutí:This chapter first introduces the basic technologies related to input/output (I/O) interface design, and describes the methods of data error detection and correction. It then gives some I/O interface design examples, including the universal asynchronous receiver transmitter (UART), personal system/2 (PS/2) keyboard and mouse, video graphics array (VGA) controller, inter integrated circuit (I2C) serial bus, and peripheral component interconnect (PCI) parallel bus. Data bit errors may occur during data transmission from the source to a receiver due to some reasons, the communication channel noise for instance. The chapter also introduces two error detection techniques, such as parity check and cyclic redundancy check (CRC), and an error correction technique such as extended Hamming code. Parity check technique can detect 1‐bit error but cannot know which bit is the error bit. The chapter finally presents the Verilog hardware description language (HDL) code for implementing the full‐duplex UART.
ISBN:1118841093
9781118841099
DOI:10.1002/9781118841105.ch14