Bit‐parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware...

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Veröffentlicht in:	IET circuits, devices & systems Jg. 12; H. 4; S. 315 - 325
Hauptverfasser:	Mathe, Sudha Ellison, Boppana, Lakshmi
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Stevenage The Institution of Engineering and Technology 01.07.2018 John Wiley & Sons, Inc
Schlagworte:	Algorithms application specific integrated circuit Application specific integrated circuits ASIC bit-parallel systolic multiplier Complexity computational complexity Computer program integrity cryptographic algorithms Cryptography Data encryption Delay delay complexity analysis Design Field programmable gate arrays field-programmable gate array Fields (mathematics) finite field multiplications FPGA Hardware Integrated circuits irreducible trinomials m-bit systolic multiplier modified interleaved multiplication algorithm Multipliers multiplying circuits Polynomials Power management power-delay products precomputation technique SMT structure
ISSN:	1751-8598, 1751-858X, 1751-8598
Online-Zugang:	Volltext
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