FPGA Based Highly Efficient AES Implementation

This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND ga...

Full description

Bibliographic Details

Published in:	Lecture notes in engineering and computer science Vol. 2231/2232; p. 5
Main Authors:	Zhang, Yong, Zhou, Fang, Wu, Ning, Yasir
Format:	Journal Article
Language:	English
Published:	Hong Kong International Association of Engineers 25.10.2017
Subjects:	Gates (circuits)
ISSN:	2078-0958, 2078-0966
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!