합성곱 신경망 연산을 위한 저전력 콘볼루션 레이어 하드웨어 설계

Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of co...

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Bibliographic Details
Published in:한국정보통신학회논문지 Vol. 28; no. 7; pp. 887 - 890
Main Authors: 박은평(Eunpyoung Park), 박종수(Jongsu Park)
Format: Journal Article
Language:Korean
Published: 한국정보통신학회 01.07.2024
Subjects:
전자/정보통신공학
CNN
Low-Power
Multiplication
Convolution Layer
ISSN:2234-4772, 2288-4165
Online Access:Get full text
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Summary:Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of convolutional neural network processing. This paper presents a convolution layer hardware using processing elements with a low-power multiplier. The low-power multiplier reduces the switching activity by increasing the exchange rate between the multiplier and multiplicand. The proposed convolution layer hardware was implemented on the Intel DE1-SoC FPGA Board using Verilog-HDL. The performance was verified by comparing the exchange rate with the existing multipliers when performing multiplications to process convolutional operations for the MNIST image database. KCI Citation Count: 0
Bibliography:http://jkiice.org
ISSN:2234-4772
2288-4165
DOI:10.6109/jkiice.2024.28.7.887