FPGA architecture for real-time information extraction and feature-based classification in image processing
The field of computer vison has made great strides toward the goal of image understanding. Today computer-vison applications can accurately track and recognize large databases of objects, can interpret scenes and guide unmanned vehicles through the most challenging environments. However, as image re...
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| Format: | Dissertation |
| Sprache: | Englisch |
| Veröffentlicht: |
ProQuest Dissertations & Theses
01.01.2015
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| ISBN: | 136909566X, 9781369095661 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | The field of computer vison has made great strides toward the goal of image understanding. Today computer-vison applications can accurately track and recognize large databases of objects, can interpret scenes and guide unmanned vehicles through the most challenging environments. However, as image resolutions continue to increase, and databases of recognizable objects become larger and more varied, image-processing algorithms demand not only higher performance but also higher classification accuracy and more complex analysis methods. The increasing computationally complex requirements of computer-vision algorithms coupled with the need for remote onboard processing of automated systems have rendered conventional computing platforms non-optimal and in some cases obsolete due to their inability to perform real-time, low-power processing. In this study we develop a framework architecture for mapping information-extraction and feature-based classification applications, as part of the image-processing domain, to programmable hardware using FPGA technology, and at the same time provide an optimal platform for embedded computer-vision applications that demand low power and a small form factor. Our proposed methods leverage the inherent parallelism of image-processing algorithms and efficiently parallelize them by creating custom-pipelined architectures on multiple FPGA platforms. We start by designing the custom architectures required to extract information at the pixel level (low-level computer vision) through image-segmentation, edge detection, and feature-extraction applications. We then development an architecture for more complex, high-level object-classification applications, using the SURF algorithm as a test case. Finally, we provide a general design methodology for developing custom hardware architectures fine-tuned to the computational demands of feature-based extraction and classification methods. Our study delivers a low-power reconfigurable platform that can meet the demands of compute-intensive vision applications, while also enabling application acceleration with respect to conventional CPU and GPU platforms. |
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| Bibliographie: | SourceType-Dissertations & Theses-1 ObjectType-Dissertation/Thesis-1 content type line 12 |
| ISBN: | 136909566X 9781369095661 |