An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA
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| Vydáno v: | IEEE Transactions on Circuits and Systems II: Express Briefs Ročník 66; s. 472 - 476 |
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| Hlavní autoři: | , , , , |
| Médium: | Journal Article |
| Jazyk: | japonština |
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Institute of Electrical and Electronics Engineers (IEEE)
01.03.2019
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| ISSN: | 1549-7747, 1558-3791 |
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| Author | Cong-Kha Pham Trong-Thuc Hoang Xuan-Thuan Nguyen Hong-Thu Nguyen Katsumi Inoue |
|---|---|
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| DOI | 10.48550/arxiv.1804.02330 10.1109/tcsii.2018.2849925 |
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| SubjectTerms | Computer Science - Hardware Architecture FOS: Computer and information sciences Hardware Architecture (cs.AR) |
| Title | An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA |
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