An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA
Saved in:
| Published in: | IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 66; pp. 472 - 476 |
|---|---|
| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | Japanese |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
01.03.2019
|
| Subjects: | |
| ISSN: | 1549-7747, 1558-3791 |
| Online Access: | Get full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Author | Cong-Kha Pham Trong-Thuc Hoang Xuan-Thuan Nguyen Hong-Thu Nguyen Katsumi Inoue |
|---|---|
| Author_xml | – sequence: 1 fullname: Xuan-Thuan Nguyen – sequence: 2 orcidid: 0000-0002-4078-0836 fullname: Trong-Thuc Hoang – sequence: 3 fullname: Hong-Thu Nguyen – sequence: 4 fullname: Katsumi Inoue – sequence: 5 orcidid: 0000-0001-5255-4919 fullname: Cong-Kha Pham |
| BackLink | https://cir.nii.ac.jp/crid/1873116917384489216$$DView record in CiNii |
| BookMark | eNotjktLAzEYRYNUsNb-AHdZuM0078cylrYWWivSvWQmXzBSMzAziv57p9TNvXdxuJxbNCltAYTuGa2kVYouQveTvytmqawoF4JeoSlTyhJhHJuct3TEGGlu0Lzvc00pd04oxafo2Re8Sik3GcqAt4sD9l3zngdohq8OcGo7_Or35DH0EPGyLcOIER9jB30f6hPgPXy23S9uC16_bPwduk7h1MP8v2fouF4dl09kd9hsl35HPpzSZFRuuIqUB-Zq4NYKpmuplR6trErBBJ2cjhZMqKUExcAIpS1ILVMThRMz9HC5LTm_NfmczBrBmHbMCCuldZxp8Qc6fE9D |
| ContentType | Journal Article |
| DBID | RYH |
| DOI | 10.48550/arxiv.1804.02330 10.1109/tcsii.2018.2849925 |
| DatabaseName | CiNii Complete |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1558-3791 |
| EndPage | 476 |
| GroupedDBID | 0R~ 29I 4.4 6IK 6J9 97E AAJGR AASAJ AAWTH ABAZT ABQJQ ABVLG ACIWK AGQYO AHBIQ AKJIK AKQYR ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ EBS EJD IFIPE IPLJI JAVBF M43 OCL PZZ RIA RIE RNS RXW RYH TAE TAF |
| ID | FETCH-LOGICAL-j956-550c25d02a19be288316b465699385fa7a6f96d8e7ab44e51e73568e464fcd393 |
| ISSN | 1549-7747 |
| IngestDate | Mon Nov 10 09:16:08 EST 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Language | Japanese |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-j956-550c25d02a19be288316b465699385fa7a6f96d8e7ab44e51e73568e464fcd393 |
| ORCID | 0000-0002-4078-0836 0000-0001-5255-4919 |
| OpenAccessLink | https://cir.nii.ac.jp/crid/1873116917384489216 |
| PageCount | 5 |
| ParticipantIDs | nii_cinii_1873116917384489216 |
| PublicationCentury | 2000 |
| PublicationDate | 2019-03-01 |
| PublicationDateYYYYMMDD | 2019-03-01 |
| PublicationDate_xml | – month: 03 year: 2019 text: 2019-03-01 day: 01 |
| PublicationDecade | 2010 |
| PublicationTitle | IEEE Transactions on Circuits and Systems II: Express Briefs |
| PublicationYear | 2019 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Publisher_xml | – name: Institute of Electrical and Electronics Engineers (IEEE) |
| SSID | ssib002993552 ssib008498160 ssib053388605 ssib018287516 ssib030782262 ssib021069338 ssib058575013 ssib002806264 ssib006262445 ssib000540814 ssib006554080 ssib019020929 ssj0029032 ssib020738464 ssib006554079 ssib011928587 ssib025517775 |
| Score | 2.3299062 |
| SourceID | nii |
| SourceType | Publisher |
| StartPage | 472 |
| SubjectTerms | Computer Science - Hardware Architecture FOS: Computer and information sciences Hardware Architecture (cs.AR) |
| Title | An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA |
| URI | https://cir.nii.ac.jp/crid/1873116917384489216 |
| Volume | 66 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1558-3791 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0029032 issn: 1549-7747 databaseCode: RIE dateStart: 20040101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Lj9MwELaWhQMcEE_xWpQDtyht7MSJfQyrLluh7a5QD72hxHGWrFCK-lL3z_JbmLHTxO0iAQcuVutUaerpvGe-IeSDjEVS0VIHlVKYZgQ5KBMgCPZ4liUvQEnEZthEOpmI2UxeHR393PXCbL6nTSO2W_njv5Ia9oDY2Dr7D-Tubgob8BqIDiuQHda_InzW4Ljk2jQ6-mO4z6WfudkCrCv8kl0EH0F_lb5Bp2pWQVaWZhoKNlJdYPXtLaYRzq4-Za75iq6hxUO3_RAm13BaL9Qa8w-mCtQioPvjMcYaRltTZ4shCF111vtsnTfB9Bus_uR6fds3o00X8-Yaryj_fJ63OtXU9trtg49_zldwsDXIuPlau-EL7JiK3PDFXknEyEz-6VASRt0goGWHzmhC0fhjd4GSVmzHEvwEi9050O0eh79cameB7WR94grr2A4NavV-bOfQHKoUg_iGCnOxrTcDKhAXl0U2l3RX_Rj01pVa1jVWDYoBKH8pGb9H7rOUS2r7C_fMZeFksTHL7fY1g6kA5mBvfsJF5mInJRzhE-X-e0cew5cL2ru_FKx5wXtznOKwA967B2AbstAxlxmIfzBPu-dhNExk1Mtr8EZpmvbmZ2TMzR5-EjwJIRx3meM0WOPOtwERGZoBgh31dk1toRzePUNbkmDIMTwkBhiGTV07huH0CXncenReZjnxKTm6yZ-RRw7O53MyyRqv40lvPLz0XI70gCO9jiO933CkZznSmzcecuQLMj0bTU_Pg3aQSXCDMJ_wxIrxMmQ5lYXG8d40KRCnEMgreJWneVLJpBQ6zYs41pzqNOKJ0HD0lSojGb0kx8280a-IJ6UCErOCqxjuIFmRVKJUFa-KlIWaRa_JCRzEV1XjSkUaUQTDQjLGQjKavPnD9bfkYc-k78jxarHWJ-SB2qzq5eK9-ff-AoBktUE |
| linkProvider | IEEE |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=An+Efficient+I%2FO+Architecture+for+RAM-Based+Content-Addressable+Memory+on+FPGA&rft.jtitle=IEEE+Transactions+on+Circuits+and+Systems+II%3A+Express+Briefs&rft.au=Xuan-Thuan+Nguyen&rft.au=Trong-Thuc+Hoang&rft.au=Hong-Thu+Nguyen&rft.au=Katsumi+Inoue&rft.date=2019-03-01&rft.pub=Institute+of+Electrical+and+Electronics+Engineers+%28IEEE%29&rft.issn=1549-7747&rft.eissn=1558-3791&rft.volume=66&rft.spage=472&rft.epage=476&rft_id=info:doi/10.48550%2Farxiv.1804.02330&rft_id=info:doi/10.1109%2Ftcsii.2018.2849925 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1549-7747&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1549-7747&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1549-7747&client=summon |