Nguyen, X., Hoang, T., Nguyen, H., Inoue, K., & Pham, C. (2019). An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs, 66, 472-476. https://doi.org/10.48550/arxiv.1804.02330
Citace podle Chicago (17th ed.)Nguyen, Xuan-Thuan, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, a Cong-Kha Pham. "An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA." IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2019): 472-476. https://doi.org/10.48550/arxiv.1804.02330.
Citace podle MLA (9th ed.)Nguyen, Xuan-Thuan, et al. "An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA." IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, 2019, pp. 472-476, https://doi.org/10.48550/arxiv.1804.02330.