Low-Power Reconfigurable FIR Filter HDL Design

This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-u...

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Bibliographic Details
Published in:Applied Electronics, AE, International Conference on pp. 1 - 6
Main Authors: Bagin, Richard, Nagy, Lukas, Stopjakova, Viera
Format: Conference Proceeding
Language:English
Published: IEEE 08.09.2025
Subjects:
Fabrication
Finite impulse response filters
FIR filter
Flip-flops
floating-point
Hardware
Hardware design languages
HDL
MATLAB
MATLAB app designer
Nanoscale devices
Power demand
Production
Q-format
SystemVerilog
Testing
ISSN:1805-9597
Online Access:Get full text
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Summary:This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-user is then capable of changing the number of active coefficients (filter order) and their value. All flip-flops can be rearranged into 1-bit scan-chain for production test, and it can also be used for filter debugging. MATLAB application was developed for easier interaction with the FIR filter. It allows the user to set the coefficients, process the samples, scan and display the contents of flip-flops.
ISSN:1805-9597
DOI:10.1109/AE66163.2025.11197774