Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract
This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-a...
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| Vydáno v: | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition s. 1 - 2 |
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31.03.2025
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| ISSN: | 1558-1101 |
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| Abstract | This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-art mid-size SoC design, we demonstrate the proposed solution is able to analyze and verify address maps of complex SoC designs and to identify the causes of discrepancies. |
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| AbstractList | This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-art mid-size SoC design, we demonstrate the proposed solution is able to analyze and verify address maps of complex SoC designs and to identify the causes of discrepancies. |
| Author | Arts, Bas Mook, Niels De Kock, Erwin Van Deursen, Arie Chakraborty, Soham |
| Author_xml | – sequence: 1 givenname: Niels surname: Mook fullname: Mook, Niels email: niels.mook@nxp.com organization: NXP,Eindhoven,The Netherlands – sequence: 2 givenname: Erwin surname: De Kock fullname: De Kock, Erwin email: erwin.de.kock@nxp.com organization: NXP,Eindhoven,The Netherlands – sequence: 3 givenname: Bas surname: Arts fullname: Arts, Bas email: bas.arts@nxp.com organization: NXP,Eindhoven,The Netherlands – sequence: 4 givenname: Soham surname: Chakraborty fullname: Chakraborty, Soham email: s.s.chakraborty@tudelft.nl organization: Delft University of Technology,Delft,The Netherlands – sequence: 5 givenname: Arie surname: Van Deursen fullname: Van Deursen, Arie email: arie.vandeursen@tudelft.nl organization: Delft University of Technology,Delft,The Netherlands |
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| Snippet | This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation... |
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| SubjectTerms | Analytical models Europe Formal verification System-on-chip |
| Title | Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract |
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