High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding

The H.264/AVC inter-prediction is performed for variable block-size motion estimation (VBSME) such as 16times16, 16times8, 8times16, 8times8, 8times4, 4times8 and 4times4, it cause the high complexity for H.264 motion estimation (ME). This investigation develops an architecture for a combined fast m...

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Vydáno v:2008 Tenth IEEE International Symposium on Multimedia s. 124 - 129
Hlavní autoři: Tsung-Han Tsai, Yu-Nan Pan
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.12.2008
Témata:
Automatic voltage control
Computer architecture
fast block matching algorithm
Frequency
H.264
Hardware
high efficiency architecture
IEC
ISO
Motion estimation
QFHD
Transform coding
Video coding
Video compression
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Shrnutí:The H.264/AVC inter-prediction is performed for variable block-size motion estimation (VBSME) such as 16times16, 16times8, 8times16, 8times8, 8times4, 4times8 and 4times4, it cause the high complexity for H.264 motion estimation (ME). This investigation develops an architecture for a combined fast motion estimation algorithm with edge information mode decision (EIMD) and predict hexagon search (PHS). Compared with other popular ME architecture, the proposed architecture has a large search range and low processing frequency. For the general specification of SDTV (720times480) with 4 reference frames, search range 256times256, the proposed architecture needs only 18.66 MHz. For the very high specification of QFHD (3840times2160) with 1 reference frame, search range 256times256, the proposed architecture only requires 112 MHz. The gate count of the proposed architecture is 300 K, and the memory usage is 12.6 KB.
DOI:10.1109/ISM.2008.98