Low power optimization of instruction cache based on tag check reduction

In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on nearly every clock cycle. This paper proposes a low power optimization method of instruction cache based on tag check reduction. By using th...

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Veröffentlicht in:	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) S. 1 - 3
Hauptverfasser:	Quanquan Li, Lidan Bao, Tiejun Zhang, Chaohuan Hou
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.10.2012
Schlagworte:	Arrays compiler support Degradation Digital signal processing low power instruction cache Microprocessors Optimization Power demand Program processors tag check reduction
ISBN:	9781467324748, 1467324744
Online-Zugang:	Volltext
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