Early estimation of aging in the design flow of integrated circuits through a programmable hardware module

Integrated circuits' aging is recognized as a key reliability bottleneck and its estimation at design time becomes mandatory to guarantee performance and lifetime of the circuit. Current approaches for the estimation of aging rely on simulation tools which integrate aging models implemented as...

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Vydáno v:Proceedings (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems) s. 1 - 6
Hlavní autoři: Sandionigi, Chiara, Altieri, Mauricio, Heron, Olivier
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.10.2017
Témata:
Aging
Estimation
Integrated circuit modeling
Propagation delay
Protocols
Stress
Transistors
ISSN:2377-7966
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Shrnutí:Integrated circuits' aging is recognized as a key reliability bottleneck and its estimation at design time becomes mandatory to guarantee performance and lifetime of the circuit. Current approaches for the estimation of aging rely on simulation tools which integrate aging models implemented as equations or look-up tables. Nevertheless, the difficulty in knowing the technological parameters involved in the estimation of aging and the necessity of accurate aging models make the modelling of the aging effects a long and hard process. This paper presents a novel solution to estimate the timing degradation on a circuit under aging conditions without the need of characterizing the aging-related technological parameters and without aging models. The solution is based on a programmable hardware module that allows observing the impact of aging directly on the paths of the circuit on a selected technology. The preliminary experimental results prove the feasibility of the solution.
ISSN:2377-7966
DOI:10.1109/DFT.2017.8244451