Fast decoding algorithm for first order DC-input sigma-delta modulators

In this paper, a new decoding technique is described for first order low frequency sigma-delta modulators. This technique, with less number of operations than available decoders, is proposed for low speed sensing devices in lab-on-chip applications. The decoding process is based on an iterative dyna...

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Bibliographic Details
Published in:2007 50th Midwest Symposium on Circuits and Systems pp. 1380 - 1383
Main Authors: Miled, M.A., Ghafar-Zadeh, E., Sawan, M.
Format: Conference Proceeding
Language:English
Published: IEEE 01.08.2007
Subjects:
Delta-sigma modulation
Dynamic range
Finite impulse response filter
Frequency modulation
Heuristic algorithms
Iterative algorithms
Iterative decoding
Laboratories
Signal restoration
Signal to noise ratio
ISBN:1424411750, 9781424411757
ISSN:1548-3746
Online Access:Get full text
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Summary:In this paper, a new decoding technique is described for first order low frequency sigma-delta modulators. This technique, with less number of operations than available decoders, is proposed for low speed sensing devices in lab-on-chip applications. The decoding process is based on an iterative dynamic decoding algorithm. The simulation results present significant improvement in term of number of operations when applied to a first-order sigma-delta modulator. The gain in the term of number of iterations is 4.013 dB for an 8-bit sequence and 1.697 dB for an 80-bit sequence.
ISBN:1424411750
9781424411757
ISSN:1548-3746
DOI:10.1109/MWSCAS.2007.4488805