Online error detection in SRAM based FPGAs using Scalable Error Detection Coding

SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC...

Full description

Saved in:
Bibliographic Details
Published in:2013 5th Asia Symposium on Quality Electronic Design (ASQED) pp. 321 - 324
Main Authors: Siddiqui, Zahid Ali, Jeong-A Lee
Format: Conference Proceeding
Language:English
Published: IEEE 01.08.2013
Subjects:
Encoding
error detection coding
Fault tolerance
Field programmable gate arrays
FPGA
Generators
Logic gates
Look-up table function
Programming
self-checking circuits
Table lookup
Tunneling magnetoresistance
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC scheme partitions the data into segments of 2-, 3- and 4-bits data and encodes these segments using SEDC codes, in parallel fashion. The programming device generates the SEDC check bits and stores them on the FPGA's SRAM cells. A high speed, compact and easily scalable online SEDC check bit generator generates the SEDC check bits, which are compared with the pre-stored check bits during circuit operation. All unidirectional errors in SRAM cells, caused by cosmic radiations, are detected. The proposed technique achieves significant improvement in area as well as speed over Berger & simple TMR technique for the same application.
AbstractList SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC scheme partitions the data into segments of 2-, 3- and 4-bits data and encodes these segments using SEDC codes, in parallel fashion. The programming device generates the SEDC check bits and stores them on the FPGA's SRAM cells. A high speed, compact and easily scalable online SEDC check bit generator generates the SEDC check bits, which are compared with the pre-stored check bits during circuit operation. All unidirectional errors in SRAM cells, caused by cosmic radiations, are detected. The proposed technique achieves significant improvement in area as well as speed over Berger & simple TMR technique for the same application.
Author Siddiqui, Zahid Ali
Jeong-A Lee
Author_xml – sequence: 1
  givenname: Zahid Ali
  surname: Siddiqui
  fullname: Siddiqui, Zahid Ali
  email: szahid@neduet.edu.pk
  organization: Dept. of Comput. Eng., Chosun Univ., Gwangju, South Korea
– sequence: 2
  surname: Jeong-A Lee
  fullname: Jeong-A Lee
  email: jalee@chosun.ac.kr
  organization: Dept. of Comput. Eng., Chosun Univ., Gwangju, South Korea
BookMark eNo9j9FKwzAYRiMoqLMvoDd5gdb8TZo0l6XrpjDZtLsfSfNXIjWVpl749o45vPouDufAd0suwxiQkHtgGQDTj1X72iyznAHPpBRcMnlBEq1KEEpr4JDDNUli_GCMgVKFKOGG7LZh8AEpTtM4UYczdrMfA_WBtm_VC7UmoqOr3bqK9Dv68E7bzgzGDkibk7L8V-rRHfkduerNEDE574LsV82-fko32_VzXW1Sr9mcmk5DLxELaaXrLS-cVsCEctIVR5RzjoIDVyYvGXLFStFbx6zkBg1Y4fiCPPxlPSIevib_aaafw_k2_wUVck69
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ASQED.2013.6643606
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781479913121
1479913146
9781479913145
147991312X
EndPage 324
ExternalDocumentID 6643606
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AAWTH
ADFMO
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
IEGSK
IERZE
OCL
RIE
RIL
ID FETCH-LOGICAL-i90t-ac91f6ee56b6dfb35d971047d6d5c91233e43137a280e37084fbd0b63aea1b4d3
IEDL.DBID RIE
IngestDate Wed Aug 27 04:56:14 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i90t-ac91f6ee56b6dfb35d971047d6d5c91233e43137a280e37084fbd0b63aea1b4d3
PageCount 4
ParticipantIDs ieee_primary_6643606
PublicationCentury 2000
PublicationDate 2013-Aug.
PublicationDateYYYYMMDD 2013-08-01
PublicationDate_xml – month: 08
  year: 2013
  text: 2013-Aug.
PublicationDecade 2010
PublicationTitle 2013 5th Asia Symposium on Quality Electronic Design (ASQED)
PublicationTitleAbbrev ASQED
PublicationYear 2013
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0001775481
Score 1.5195937
Snippet SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors...
SourceID ieee
SourceType Publisher
StartPage 321
SubjectTerms Encoding
error detection coding
Fault tolerance
Field programmable gate arrays
FPGA
Generators
Logic gates
Look-up table function
Programming
self-checking circuits
Table lookup
Tunneling magnetoresistance
Title Online error detection in SRAM based FPGAs using Scalable Error Detection Coding
URI https://ieeexplore.ieee.org/document/6643606
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV27TsMwFLVKxcAEqEW85YERt26c2PEY9QEDVIF26Fb5cYO6JChN-X5st7RCYmGzbF1bsmWdK_uccxF6SFxKQCNJibtohsTacqKkNkRq4Vm6hbUmVC15EdNpuljIvIUe91oYAAjkM-j5ZvjLt5XZ-KeyPnfwyb2_9pEQfKvVOryneCu3dPCji6Gyn83exiNP3mK9XeCvCioBQCan_1v6DHUPSjyc7zHmHLWg7KB86w-Koa6rGltoAp2qxKsSz96zV-yRyeJJ_pStsee1f-CZOwmvkcLjEDLahwwrP28XzSfj-fCZ7CojkJWkDVFGDgoOkHDNbaFZYqXwlguW28QNRYyBywuYUFFKgQmaxoW2VHOmQA10bNkFapdVCZcIO7h3N9CLOWIaA-c6sopr6dI4aZjiyRXq-M1Yfm69L5a7fbj-u_sGnUShXIQnyN2idlNv4A4dm69mta7vw4F9A2tKlgI
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT8IwFG-ImuhJDRi_7cGjg7Ju3XokfIgRyBQO3Ei7vhkumxnDv9--ghATL96WLW9N2jS_l_b3QchjaFsC5kvm2Y2WeoE2wlNSp57UEbJ0M2NSl1oyiiaTeD6XSY087bQwAODIZ9DER3eXb4p0jUdlLWHhU6C_9iEmZ8mNWmt_ooJmbnH7RxnDZKszfev3kL7Fm9vSXxkqDkIGp_8b_Iw09lo8muxQ5pzUIK-TZOMQSqEsi5IaqByhKqfLnE7fO2OK2GToIHnurCgy2z_o1K4FqqRo35X0diXdAv_bILNBf9YdettsBG8pWeWpVLYzARAKLUymeWhkhKYLRpjQfvI5B9sZ8Ej5MQMesTjItGFacAWqrQPDL8hBXuRwSagFfLsHUc4RsACE0L5RQkvbyMmUKxFekTpOxuJz436x2M7D9d-vH8jxcDYeLUYvk9cbcuK78Aiky92Sg6pcwx05Sr-q5aq8d4v3DXnOmVE
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2013+5th+Asia+Symposium+on+Quality+Electronic+Design+%28ASQED%29&rft.atitle=Online+error+detection+in+SRAM+based+FPGAs+using+Scalable+Error+Detection+Coding&rft.au=Siddiqui%2C+Zahid+Ali&rft.au=Jeong-A+Lee&rft.date=2013-08-01&rft.pub=IEEE&rft.spage=321&rft.epage=324&rft_id=info:doi/10.1109%2FASQED.2013.6643606&rft.externalDocID=6643606