FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption

AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation o...

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Vydané v:2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) s. 1769 - 1776
Hlavní autori: Srinivas, N. S. Sai, Akramuddin, Md
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.03.2016
Predmet:
Advanced Encryption Standard (AES)
Algorithm design and analysis
Clocks
Cryptography
Decryption
Encryption
Field Programmable Gate Array (FPGA)
Field programmable gate arrays
Hardware Description Language (HDL)
Rijndael
Table lookup
Timing
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Popis
Shrnutí:AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation of AES Rijndael Encryption and Decryption Algorithm by using Xilinx Virtex-7 FPGA. The hardware design approach is entirely based on pre-calculated look-up tables (LUTs) which results in less complex architecture, thereby providing high throughput and low latency. There are basically three different formats in AES. They are AES-128, AES-192 and AES-256. The encryption and decryption blocks of all the three formats are efficiently designed by using Verilog-HDL and are synthesized on Virtex-7 XC7VX690T chip (Target Device) with the help of Xilinx ISE Design Suite-14.7 Tool. The synthesis tool was set to optimize speed, area and power. The power analysis is made by using Xilinx XPower Analyzer. Pre-calculated LUTs are used for the implementation of algorithmic functions, namely S-Box and Inverse S-Box transformations and also for GF (2 8 ) i.e. Galois Field Multiplications involved in Mix-Columns and Inverse Mix-Columns transformations. The proposed architecture is found to be having good efficiency in terms of latency, throughput, speed/delay, area and power.
DOI:10.1109/ICEEOT.2016.7754990