Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming

The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. T...

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Published in:2017 Internet Technologies and Applications (ITA) pp. 181 - 184
Main Authors: Fedosenko, Yuriy S., Reznikov, Mikhail B., Plekhov, Aleksandr S., Chakirov, Roustiam, Houlden, Nigel
Format: Conference Proceeding
Language:English
Published: IEEE 01.09.2017
Subjects:
calculations modeling
Computational modeling
discrete optimisation
Dispatching
dispatching problem
Dynamic programming
Field programmable gate arrays
Graphics processing units
massively parallel calculations
Random access memory
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Abstract The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order.
AbstractList The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order.
Author Chakirov, Roustiam
Fedosenko, Yuriy S.
Reznikov, Mikhail B.
Plekhov, Aleksandr S.
Houlden, Nigel
Author_xml – sequence: 1
  givenname: Yuriy S.
  surname: Fedosenko
  fullname: Fedosenko, Yuriy S.
  organization: Volga State Univ. of Water Transp., Nizhny Novgorod, Russia
– sequence: 2
  givenname: Mikhail B.
  surname: Reznikov
  fullname: Reznikov, Mikhail B.
  organization: Volga State Univ. of Water Transp., Nizhny Novgorod, Russia
– sequence: 3
  givenname: Aleksandr S.
  surname: Plekhov
  fullname: Plekhov, Aleksandr S.
  organization: Alekseev Nizhny Novgorod State Tech. Univ., Nizhny Novgorod, Russia
– sequence: 4
  givenname: Roustiam
  surname: Chakirov
  fullname: Chakirov, Roustiam
  organization: Bonn-Rhein-Sieg Univ. of Appl. Sci., St. Augustin, Germany
– sequence: 5
  givenname: Nigel
  surname: Houlden
  fullname: Houlden, Nigel
  organization: Glyndwr Univ., Wrexham, UK
BookMark eNotkEFugzAQRV2pXTRpT5CNLwAdYzvgZYTSJlKkLso-MsYGS8amYFXl9oU0q_ma_-YtZoMeffAaoR2BlBAQb-fqWJ4OaQYkTwsCRFD2gDaEgwBWEM6e0feXks76Fksv3TzZCQeDp-B-bjvXhtHGrp-wCSNWctHbhcfDGGqn-5Vt7DTIqLqVtx7HTmMVfNS_8dbOXvZWrQftKPt-oV7Qk5Fu0q_3uUXV-7EqT8nl8-NcHi6JFRCTPTW64YzvBc_AMGCKU0olITlRsIYGRG64kcoIxeusUIXRoFjeiEZALegW7f61Vmt9HUbby3G-3p9A_wC-IlkF
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ITECHA.2017.8101934
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 1509048154
9781509048151
EndPage 184
ExternalDocumentID 8101934
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i90t-63fed54569520f404c5333a1171c033a1d097f5facf9c5b28c8fe0c47d9d90b93
IEDL.DBID RIE
IngestDate Thu Jun 29 18:37:28 EDT 2023
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i90t-63fed54569520f404c5333a1171c033a1d097f5facf9c5b28c8fe0c47d9d90b93
PageCount 4
ParticipantIDs ieee_primary_8101934
PublicationCentury 2000
PublicationDate 2017-Sept.
PublicationDateYYYYMMDD 2017-09-01
PublicationDate_xml – month: 09
  year: 2017
  text: 2017-Sept.
PublicationDecade 2010
PublicationTitle 2017 Internet Technologies and Applications (ITA)
PublicationTitleAbbrev ITECHA
PublicationYear 2017
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.6446258
Snippet The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The...
SourceID ieee
SourceType Publisher
StartPage 181
SubjectTerms calculations modeling
Computational modeling
discrete optimisation
Dispatching
dispatching problem
Dynamic programming
Field programmable gate arrays
Graphics processing units
massively parallel calculations
Random access memory
Title Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming
URI https://ieeexplore.ieee.org/document/8101934
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT8IwFG-AePCkBozf6cGjg3ZraXs0RMLBEBKJ4UbWL10iTGHw9_vaLRgTL97a7i1bXr9-3X7v9xC61zIzjniY39wPE0YlSbTIWWL1UFjtPc-iqM_rs5hO5WKhZi30cIiFcc5F8pnrh2L8l29LswufygZBjEplrI3aQog6VqsREqJEDWCqjyaPga0l-o3lr5QpcccYn_zvWaeo9xN6h2eHTeUMtdy6i75ewJNQxXkjIYJLj2HQ7GPbx1sJJ_z31RYDAMXgqjLGOuImV0ywtQUsHFWkTeJijQH04cBRh4U5Xq2z0uOGq7UCqx6aj5_mo0nS5EpICkWqZJh5ZwMYUjwlnhFmAMZlOaWCGhIKlijhuc-NV4brVBrpHTFMWGUV0So7Rx14O3eBsMzhHmspQEPKuOOKBhKclkRJLlOdXqJu8Nbys1bDWDaOuvq7-Rodhw6pWVk3qFNtdu4WHZl9VWw3d7ELvwFMFKDu
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1bT8IwFG4QTfRJDRjv9sFHB-3WsvbREAlGJCQSwxtZb0oiTGHw-z3tFoyJL7613Vm2nN6-bt_5DkK3SiTaEgfzm7tOxKggkUozFhnVSY1yjidB1Od1kA6HYjKRoxq628bCWGsD-cy2fDH8yze5XvtPZW0vRiUTtoN2OWMxLaO1KikhSmQbJnu3f-_5Wmmrsv2VNCXsGb3D_z3tCDV_gu_waLutHKOaXTTQ1wv4Eqo4q0REcO4wDJtNaPt4y-GM_z5fYYCgGJyVh2hHXGWL8bZmBktHEYiTeLbAAPuwZ6nD0hyulnnpccXWmoNVE417D-NuP6qyJUQzSYqokzhrPBySPCaOEaYByCUZpSnVxBcMkanjLtNOaq5ioYWzRLPUSCOJkskJqsPb2VOERQb3GEMBHFLGLZfU0-CUIFJwEav4DDW8t6afpR7GtHLU-d_NN2i_P34eTAePw6cLdOA7p-RoXaJ6sVzbK7SnN8VstbwO3fkN1c2kNQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2017+Internet+Technologies+and+Applications+%28ITA%29&rft.atitle=Scaling+analysis+of+solving+algorithms+for+canonical+problem+of+dispatching+in+the+context+of+dynamic+programming&rft.au=Fedosenko%2C+Yuriy+S.&rft.au=Reznikov%2C+Mikhail+B.&rft.au=Plekhov%2C+Aleksandr+S.&rft.au=Chakirov%2C+Roustiam&rft.date=2017-09-01&rft.pub=IEEE&rft.spage=181&rft.epage=184&rft_id=info:doi/10.1109%2FITECHA.2017.8101934&rft.externalDocID=8101934