Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming

The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. T...

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Published in:2017 Internet Technologies and Applications (ITA) pp. 181 - 184
Main Authors: Fedosenko, Yuriy S., Reznikov, Mikhail B., Plekhov, Aleksandr S., Chakirov, Roustiam, Houlden, Nigel
Format: Conference Proceeding
Language:English
Published: IEEE 01.09.2017
Subjects:
calculations modeling
Computational modeling
discrete optimisation
Dispatching
dispatching problem
Dynamic programming
Field programmable gate arrays
Graphics processing units
massively parallel calculations
Random access memory
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Abstract The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order.
AbstractList The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order.
Author Chakirov, Roustiam
Fedosenko, Yuriy S.
Reznikov, Mikhail B.
Plekhov, Aleksandr S.
Houlden, Nigel
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  givenname: Mikhail B.
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  organization: Volga State Univ. of Water Transp., Nizhny Novgorod, Russia
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  givenname: Aleksandr S.
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  fullname: Plekhov, Aleksandr S.
  organization: Alekseev Nizhny Novgorod State Tech. Univ., Nizhny Novgorod, Russia
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  givenname: Roustiam
  surname: Chakirov
  fullname: Chakirov, Roustiam
  organization: Bonn-Rhein-Sieg Univ. of Appl. Sci., St. Augustin, Germany
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  givenname: Nigel
  surname: Houlden
  fullname: Houlden, Nigel
  organization: Glyndwr Univ., Wrexham, UK
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Snippet The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The...
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StartPage 181
SubjectTerms calculations modeling
Computational modeling
discrete optimisation
Dispatching
dispatching problem
Dynamic programming
Field programmable gate arrays
Graphics processing units
massively parallel calculations
Random access memory
Title Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming
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